(a) Field of the Invention
The present invention relates to a semiconductor device having a bonding pad and, more particularly, to the structure of a bonding pad for suppressing growth of a crack in an insulating film.
(b) Description of the Related Art
Semiconductor devices such as LSIs have bonding pads overlying active elements, such as transistor and capacitor, that are formed on a semiconductor substrate. The bonding pad is connected to an underlying active element via a contact plug and an interconnect formed within an interlevel dielectric film. The bonding pad is disposed on the outer surface of the semiconductor device, and is electrically connected to an external line via a boding wire or bump.
FIG. 5A exemplifies the structure of a bonding pad in a conventional semiconductor device, and FIG. 5B shows a sectional view taken along line B-B′ in FIG. 5A. The semiconductor device, generally designated by numeral 40, includes a first interlevel dielectric film 11 formed on underlying active elements (not shown). On the first interlevel dielectric film 11 are formed first interconnects 12 and contact pads (first pads) 12a both made of Al. A second interlevel dielectric film 13 is formed on the first interlevel dielectric film 11, first interconnects 12 and contact pads 12a. 
A plurality of contact holes 41 are formed in the second interlevel dielectric film 13, and are filled with contact plugs 42. The contact plugs 42 includes, for example, a barrier metal layer in contact with the wall of the contact hole 41, and a high-melting-point metal layer filling the contact hole 41 via the barrier metal layer.
On the second interlevel dielectric film 13 are formed second interconnects (not shown) and bonding pads (second pads) 16. The bonding pads 16 are in contact with the top of the contact plugs 42. A passivation film (cover film) 17 covers the bonding pads 16, and has openings 17a which expose a central portion of the bonding pads 16.
It is known in the conventional semiconductor device that a wafer test or bonding process applies a thrust force onto the surface of the bonding pad 16 to generate a crack in an interlevel dielectric film. FIG. 6 shows an example of the wafer test using a probe pin 21, wherein the probe pin 21 applies a thrust on the bonding pad 16 which in turn causes occurring of a crack 22 in the second interlevel dielectric film 13. The crack formed in the second interlevel dielectric film 13 may eventually grow and reach the first interconnect. In such a case, external water may enter the semiconductor device along the crack. The ingress of water causes corrosion of interconnects to degrade the reliability of the semiconductor device.
In general, the recent development of higher-integrated semiconductor devices decreases the distance between the bonding pad and the interconnect, resulting in a larger possibility that the crack incurs a malfunction on the interconnect. Thus, it is necessary to prevent occurring of the cracks especially in the higher-integrated semiconductor device.
Patent Publication JP-A-2001-85465 describes suppression of cracks by disposing the bonding pads in an array, the bonding pads having a higher concentration of a metal element having a higher rigidity. This technique improves the mechanical strength of the bonding pad area, i.e., area of the insulation film where the bonding pads are disposed.